Avago Technologies LSI8751D - Manual (Page 310)

IX-6 Index
SODR most significant byte full 5-29
software reset 5-32
source I/O memory enable 5-48
SREQ/ status 5-22
SSEL/ status 5-22
start DMA operation 5-52
start SCSI transfer 5-8
start sequence 5-4
synchronous clock conversion factor 5-12
target mode 5-6
timer test mode 5-76
TolerANT enable 5-75
Ultra enable 5-12
unexpected disconnect 5-55
,
5-58
wide SCSI receive 5-11
wide SCSI send 5-10
won arbitration 5-27
write and invalidate enable 5-38
reselected bit 5-54
,
5-57
reset SCSI offset bit 5-73
RESPID0 register 5-69
RESPID1 register 5-70
response ID one register 5-70
response ID zero register 5-69
revision level bits 5-37
S
SACK/ status bit 5-22
SATN/ active 5-57
SATN/ active bit 5-57
SATN/ status bit 5-22
SBCL register 5-22
SBDL register 5-78
SBR register 5-51
SBSY status bit 5-22
SC_D/ status bit 5-23
SCID register 5-14
SCLK bit 5-72
SCNTL0 register 5-3
SCNTL1 register 5-6
SCNTL2 register 5-9
SCNTL3 register 5-12
scratch register 5-51
scratchA register 5-47
scratchA/B operation bit 5-36
scratchB register 5-79
SCRIPTS bit 5-62
SCRIPTS interrupt instruction received bit 5-24
SCRIPTS processor 2-2
instruction prefetching 2-5
internal RAM for instruction storage 2-3
performance 2-2
SCRIPTS RAM 2-3
scratchA/B operation bit 5-36
SCSI
core 2-1
differential mode 2-20
termination 2-23
timings 7-51
TolerANT technology 1-5
SCSI ATN condition - target mode 5-54
SCSI ATN condition bit 5-54
SCSI bus control lines register 5-22
SCSI bus data lines register 5-78
SCSI bus interface 2-19
to
2-25
SCSI C_D/ signal bit 5-28
SCSI chip ID register 5-14
SCSI control enable bit 5-73
SCSI control one register 5-6
SCSI control three register 5-12
SCSI control two register 5-9
SCSI control zero register 5-3
SCSI core 2-1
SCSI data high impedance bit 5-40
SCSI destination ID register 5-18
SCSI differential mode bit 5-73
SCSI disconnect unexpected bit 5-9
SCSI FIFO test read bit 5-75
SCSI FIFO test write bit 5-77
SCSI first byte received register 5-20
SCSI gross error bit 5-54
,
5-57
SCSI high impedance mode bit 5-74
SCSI I_O/ signal bit 5-28
SCSI input data latch register 5-77
SCSI instructions
block move 6-5
I/O 6-12
load/store 6-37
memory move 6-33
read/write 6-21
transfer control 6-26
SCSI interrupt enable one register 5-55
SCSI interrupt enable zero register 5-53
SCSI interrupt pending bit 5-33
SCSI interrupt status one register 5-59
SCSI interrupt status zero register 5-56
SCSI isolation mode bits 5-72
SCSI longitudinal parity register 5-60
SCSI loopback mode bit 5-74
SCSI low level mode bit 5-74
SCSI MSG/ signal bit 5-28
SCSI output control latch register 5-21
SCSI output data latch register 5-78
SCSI parity error bit 5-55
SCSI phase mismatch bit 5-54
SCSI reset condition bit 5-55
SCSI RST/ received bit 5-58
SCSI RST/ signal bit 5-27
SCSI SCRIPTS operation 6-1
sample instruction 6-3
SCSI SDP0/ parity signal bit 5-27
SCSI SDP1 signal bit 5-30
SCSI selected as ID bits 5-70
SCSI selector ID register 5-22
SCSI status one register 5-27
SCSI status two register 5-29
SCSI status zero register 5-26
SCSI synchronous offset maximum 5-71
SCSI synchronous offset zero bit 5-71
SCSI test one register 5-72
SCSI test three register 5-75
SCSI test two register 5-73
SCSI test zero register 5-70
SCSI timer one register 5-66
SCSI timer zero register 5-64
SCSI timing diagrams 7-51
SCSI transfer register 5-15
SCSI true end of process bit 5-36
SCSI valid bit 5-22
SCSI wide residue register 5-61
SDID register 5-18