Avago Technologies LSI8751D - Manual (Page 62)

2-38 Functional Description
Block Move instruction is used, if the WSS bit is set at the start of a data
send command, the first byte of the data send command is assumed to
be the high-order byte and is “married” with the low-order byte stored in
the lower byte of the
SCSI Output Data Latch (SODL) register before the
two bytes are sent across the SCSI bus. For “N” consecutive wide data
send Block Move commands, the first through the (Nth – 1) Block Move
instructions should be Chained Block Moves.
2.6 Power Management
The LSI53C875E complies with the PCI Bus Power Management
Interface Specification, Revision 1.0. The PCI Function Power States D0,
D1, D2, and D3 are defined in that specification. D0 and D3 are required
by specification, and D1 and D2 are optional. D0 is the maximum
powered state, and D3 is the minimum powered state. Power state D3
is further categorized as D3hot or D3cold. A function that is powered off
is said to be in the D3cold power state.
The power states for the SCSI function are independently controlled
through two power state bits that are located in the PCI Configuration
Space register 0x44. The bits are encoded as:
Power states D1 and D2 are not discussed because they have not been
implemented as a new feature.
The Power states – D0 and D3 – are described below in conjunction with
each SCSI function. Power state actions are separate for each function.
2.6.1 Power State D0
Power state D0 is the maximum power state and is the power-up default
state for each function.
00b D0
01b Reserved
10b Reserved
11b D3