Avago Technologies LSI8751D - Manual (Page 228)

6-32 Instruction Set of the I/O Processor
CD Compare Data 18
When this bit is set, the first byte received from the SCSI
data bus (contained in
SCSI First Byte Received (SFBR)
register) is compared with the Data to be Compared Field
in the Transfer Control instruction. The Wait for Valid
Phase bit controls when this compare occurs. The Jump
if True/False bit determines the condition (true or false)
to branch on.
CP Compare Phase 17
When the LSI53C875 is in Initiator mode, this bit controls
phase compare operations. When this bit is set, the SCSI
phase signals (latched by SREQ/) are compared to the
Phase Field in the Transfer Control instruction. If they
match, the comparison is true. The Wait for Valid Phase
bit controls when the compare occurs. When the
LSI53C875 is operating in Target mode and this bit is set,
it tests for an active SCSI SATN/ signal.
WVP Wait For Valid Phase 16
If the Wait for Valid Phase bit is set, the LSI53C875 waits
for a previously unserviced phase before comparing the
SCSI phase and data.
If the Wait for Valid Phase bit is cleared, the LSI53C875
compares the SCSI phase and data immediately.
DCM Data Compare Mask [15:8]
The Data Compare Mask allows a SCRIPT to test certain
bits within a data byte. During the data compare, if any
mask bits are set, the corresponding bit in the
SCSI First
Byte Received (SFBR) data byte is ignored. For instance,
a mask of 01111111b and data compare value of
1XXXXXXXb allows the SCRIPTS processor to
determine whether or not the high order bit is set while
ignoring the remaining bits.
Bit 19
Result of
Compare
Action
0 False Jump Taken
0 True No Jump
1 False No Jump
1 True Jump Taken