Avago Technologies LSI8751D - Manual (Page 96)

4-4 Signal Descriptions
Figure 4.3 LSI53C875N Pin Diagram
NC
NC
NC
BYTEPAR2
AD22
AD19
AD18
AD17
FRAME/
TRDY/
V DD-I
STOP/
BYTEPAR1
AD13
V SS
AD12
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
36
37
38
39
40
AD21
V DD-I
PAR
V
SS
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
NC
NC
IDSEL
V SS
AD20
V
SS
C_BE2/
IRDY/
DEVSEL/
PERR/
C_BE1/
AD14
C_BE3/
AD23
AD16
V
SS
V
SS
V
SS
AD15
V DD-I
NC
NC
NC
SDIRP0
SD13
SDP1/
SD1/
V
SS-S
SD5/
SD7/
SATN/
V
SS-S
V SS-S
SI_0/
SD8/
V
SS-S
156
154
152
150
148
146
144
142
140
138
136
134
132
130
128
126
124
122
121
120
119
118
117
SD14/
SD15/
SRST/
SSEL/
155
153
151
149
147
145
143
141
139
137
135
133
131
129
127
125
123
NC
NC
SDIR7
SD12/
V
SS-S
SD0/
SD4/
V
SS-S
SDP0/
SACK/
SMSG/
SREQ/
NC
V
DD
SD2/
SD3/
SD6/
SBSY/
SC_D/
SD9/
NC NC NC
AD5 AD3 AD0 IRQ/
GPIO0_FETCH
TESTIN
TD0
MAD6 MAD5 MAD0 GPIO3 GPIO4
DIFFSENS
AD2 AD1
MAD3 MAD1
NC NC V
SS
V
DD-I V
SS
V
DD-C
SCLK
TMS
MAD7
V
DD
MAD2
V
SS
AD6 AD4
GPIO1_MASTER/
V
SS-C
MA
C/_TEST
OUT
MAD4
GPIO2_MAS2/
SDIRP1 SDIR15 SDIR14 MAS1 MWE/ MCE/ BIG_LIT/ GNT/ BYTEP
AR3
AD31 AD30 AD29 AD28 V
DD-I
V
SS
169 171 173 175 177 179 181 183 185 187 189 191 192 193 194 195 196 198 200 202 204 206
SDIR0 RST/ V
SS-C
AD27 AD26 AD24 NC NC
208
NC
170 172 174 176 178 180 182 184 186 188 190 197 199 201 203 205 207
V
DD
TCK SDIR12 MAS0/ MOE/ SERR/ CLK V
DD-C
V
SS
SDIR13 V
DD
TDI REQ/ V
SS
AD25 NC
53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 88 89 90 91 92 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86
LSI53C875N
PCI to SCSI I/O Processor
208-Pin
Quad Flat Pack
156
154
152
150
148
146
144
142
140
138
136
134
132
130
128
126
124
122
121
120
119
118
117
155
153
151
149
147
145
143
141
139
137
135
133
131
129
127
125
123
116
114
112
110
108
106
115
113
111
109
107
105
SD10/
V
DD
SDIR9
NC
NC
NC
SD11/
SDIR8
NC
NC
SDIR10
NC
41
43
45
47
48
49
50
51
52
42
44
46 C_BE0/
NC
NC
NC
AD9
AD8
AD10
V
SS
AD7
AD11
BYTEPAR0
NC
93 95 97 99 100 101 102 103 104 94 96 98
TGS V
DD
SDIR11
NC NC NC
RSTDIR
V
SS
SELDIR BSYDIR
NC IGS NC
NC NC SDIR6 SDIR3
157 159 161 163 165 167
NC
158 160 162 164 166 168
NC NC SDIR4 SDIR2 SDIR5 V
SS
SDIR1
Note: The decoupling capacitor arrangement shown in Figures 4.1 and 4.2 is recom-
mended to maximize the benefits of the internal split ground system. Capacitor val-
ues between 0.01 and 0.1
µ
F should provide adequate noise isolation. Because of
the number of high current drivers on the LSI53C875, a multilayer PC board with
power and ground planes is required.