Avago Technologies LSI8751D - Manual (Page 261)

PCI and External Memory Interface Timing Diagrams 7-25
Figure 7.16 Burst Opcode Fetch
CLK
GPIO0_FETCH/
GPIO1_MASTER/
REQ/
GNT/
FRAME/
C_BE/
PAR/
(Driven by System)
(Driven by LSI53C875)
(Driven by LSI53C875)
(Driven by LSI53C875)
(Driven by Arbiter)
(Driven by LSI53C875)
AD/
Target-Data)
(Driven by LSI53C875)
IRDY/
(Driven by Target)
(Driven by
LSI53C875-Addr;
Target-Data)
TRDY/
STOP/
DEVSEL/
(Driven by LSI53C875)
(Driven by Target)
(Driven by Target)
(Driven by
t
6
t
5
t
3
Data In
CMD
t
3
t
3
t
3
t
1
t
2
t
2
t
2
t
1
LSI53C875-Addr;
t
8
t
10
t
9
t
7
t
4
Addr
Out
t
1
t
2
BE
Out In In
t
1
t
3