Avago Technologies LSI8751D - Manual (Page 205)

Block Move Instructions 6-9
overwrites the DMA Byte Counter (DBC) register
with the length of the Command Descriptor Block:
6, 10, or 12 bytes.
– If the Vendor Unique Enhancement 1 (VUE1) bit
( SCSI Control Two (SCNTL2), bit 1) is set, the
LSI53C875 receives the number of bytes in the byte
count regardless of the group code.
– If the Vendor Unique Enhancement 1 bit is clear
and group code is vendor unique, the LSI53C875
receives the number of bytes in the count.
– If any other Group Code is received, the DMA Byte
Counter (DBC) register is not modified and the
LSI53C875 requests the number of bytes specified
in the
DMA Byte Counter (DBC) register. If the DMA
Byte Counter (DBC) register contains 0x000000, an
illegal instruction interrupt is generated.
4. The LSI53C875 transfers the number of bytes
specified in the DMA Byte Counter (DBC) register
starting at the address specified in the DMA Next
Address (DNAD) register. If the Opcode bit is set and
a data transfer ends on an odd byte boundary, the
LSI53C875 stores the last byte in the
SCSI Wide
Residue (SWIDE) register during a receive operation.
This byte is combined with the first byte from the
subsequent transfer so that a wide transfer can be
completed.
5. If the SATN/ signal is asserted by the Initiator or a
parity error occurred during the transfer, the transfer
can optionally be halted and an interrupt generated.
The Disable Halt on Parity Error or ATN bit in the
SCSI Control One (SCNTL1) register controls
whether the LSI53C875 halts on these conditions
immediately, or waits until completion of the current
Move.