2 second dword, 3 i/o instruction, 1 first dword – Avago Technologies LSI8751D User Manual
Page 208: Second dword, I/o instruction, First dword
6-12
Instruction Set of the I/O Processor
bytes transferred. In addition, the
register is incremented by the number of bytes
transferred. This process is repeated until the DBC
register has been decremented to zero. At that time, the
LSI53C875 fetches the next instruction.
If bit 28 is set, indicating table indirect addressing, this
field is not used. The byte count is instead fetched from
a table pointed to by the
register.
6.2.2 Second Dword
Start Address
[31:0]
This 32-bit field specifies the starting address of the data
to move to/from memory. This field is copied to the
register. When the LSI53C875
transfers data to or from memory, the DNAD register is
incremented by the number of bytes transferred.
When bit 29 is set, indicating indirect addressing, this
address is a pointer to an address in memory that points
to the data location. When bit 28 is set, indicating table
indirect addressing, the value in this field is an offset into
a table pointed to by the
.
The table entry contains byte count and address
information.
6.3 I/O Instruction
6.3.1 First Dword
IT[1:0]
Instruction Type - I/O Instruction
[31:30]
OPC[2:0]
Opcode
[29:27]
The following Opcode bit configurations have different
meanings, depending on whether the LSI53C875 is
operating in initiator or target mode.
Note:
Opcode selections 101–111 are considered Read/Write
instructions and are described in