Avago Technologies LSI8751D User Manual
Page 165
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ERL
Enable Read Line
3
This bit enables a PCI Read Line command. If PCI cache
mode is enabled by setting bits in the PCI Cache Line
Size register, this chip issues a Read Line command on
all read cycles if other conditions are met. For more
information on these conditions, refer to
ERMP
Enable Read Multiple
2
This bit causes Read Multiple commands to be issued on
the PCI bus after certain conditions have been met.
These conditions are described in
BOF
Burst Opcode Fetch Enable
1
Setting this bit causes the LSI53C875 to fetch
instructions in burst mode. Specifically, the chip bursts in
the first two Dwords of all instructions using a single bus
ownership. If the instruction is a Memory-to-Memory
Move type, the third Dword is accessed in a subsequent
bus ownership. If the instruction is an indirect type, the
additional Dword is accessed in a subsequent bus
ownership. If the instruction is a table indirect block move
type, the chip accesses the remaining two Dwords in a
subsequent bus ownership, thereby fetching the four
Dwords required in two bursts of two Dwords each. This
bit has no effect if SCRIPTS instruction prefetching is
enabled.
MAN
Manual Start Mode
0
Setting this bit prevents the LSI53C875 from
automatically fetching and executing SCSI SCRIPTS
when the
register is
written. When this bit is set, the Start DMA bit in the
register must be set to begin SCRIPTS
execution. Clearing this bit causes the LSI53C875 to
automatically begin fetching and executing SCSI
SCRIPTS when the
register is written. This bit normally is not used for SCSI
SCRIPTS operations.