9 scsi bus interface, Scsi bus interface – Avago Technologies LSI8751D User Manual
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PCI Cache Mode
2-19
Step 3.
If any wide transfers have been performed using the Chained
Move instruction, read the Wide SCSI Receive bit (
, bit 0) to determine whether a byte is left
in the
register.
Synchronous SCSI Receive –
Step 1.
If the DMA FIFO size is set to 88 bytes, subtract the seven
least significant bits of the
register
from the 7-bit value of the
register. AND
the result with 0x7F for a byte count between 0 and 88.
If the DMA FIFO size is set to 536 bytes (using bit 5 of the
register), subtract the 10 least significant
bits of the
register from the 10-bit
value of the DMA FIFO Byte Offset Counter, which consists of
bits [1:0] in the CTEST5 register and bits [7:0] of the DMA FIFO
register. AND the result with 0x3FF for a byte count between
0 and 536.
Step 2.
Read bits [7:4] of the
register and
bit 4 of the
register, the binary
representation of the number of valid bytes in the SCSI FIFO,
to determine if any bytes are left in the SCSI FIFO.
Step 3.
If any wide transfers have been performed using the Chained
Move instruction, read the Wide SCSI Receive bit (
, bit 0) to determine whether a byte is left
in the
register.
2.5.9 SCSI Bus Interface
The LSI53C875 supports both SE and differential operation.
All SCSI signals are active low. The LSI53C875 contains the SE output
drivers and can be connected directly to the SCSI bus. Each output is
isolated from the power supply to ensure that a powered down
LSI53C875 has no effect on an active SCSI bus (CMOS “voltage
feed-through” phenomena). TolerANT technology provides signal filtering
at the inputs of SREQ/ and SACK/ to increase immunity to signal
reflections.