Avago Technologies LSI8751D - Manual (Page 8)

viii Contents
2.5.4 JTAG Boundary Scan Testing 2-10
2.5.5 Big and Little Endian Support 2-10
2.5.6 Loopback Mode 2-12
2.5.7 Parity Options 2-12
2.5.8 DMA FIFO 2-15
2.5.9 SCSI Bus Interface 2-19
2.5.10 Select/Reselect During Selection/Reselection 2-25
2.5.11 Synchronous Operation 2-25
2.5.12 Ultra SCSI Synchronous Data Transfers 2-27
2.5.13 Interrupt Handling 2-28
2.5.14 Chained Block Moves 2-34
2.6 Power Management 2-38
2.6.1 Power State D0 2-38
2.6.2 Power State D3 2-39
Chapter 3 PCI Functional Description
3.1 PCI Addressing 3-1
3.1.1 PCI Bus Commands and Functions Supported 3-2
3.2 PCI Cache Mode 3-4
3.2.1 Support for PCI Cache Line Size Register 3-4
3.2.2 Selection of Cache Line Size 3-5
3.2.3 Alignment 3-5
3.2.4 Memory Move Misalignment 3-6
3.2.5 Memory Write and Invalidate Command 3-6
3.2.6 Memory Read Line Command 3-8
3.2.7 Memory Read Multiple Command 3-9
3.3 Configuration Registers 3-11
Chapter 4 Signal Descriptions
4.1 MAD Bus Programming 4-22
Chapter 5 SCSI Operating Registers
Chapter 6 Instruction Set of the I/O Processor
6.1 SCSI SCRIPTS 6-1
6.1.1 Sample Operation 6-3