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14 chained block moves, Chained block moves – Avago Technologies LSI8751D User Manual

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2-34

Functional Description

1.

Read

Interrupt Status (ISTAT)

.

2.

If the INTF bit is set, it must be written to a one to clear this status.

3.

If only the SIP bit is set, read

SCSI Interrupt Status Zero (SIST0)

and

SCSI Interrupt Status One (SIST1)

to clear the SCSI interrupt

condition and get the SCSI interrupt status. The bits in the SIST0
and SIST1 tell which SCSI interrupts occurred and determine what
action is required to service the interrupts.

4.

If only the DIP bit is set, read the

DMA Status (DSTAT)

to clear the

interrupt condition and get the DMA interrupt status. The bits in
DSTAT tell which DMA interrupts occurred and determine what
action is required to service the interrupts.

5.

If both the SIP and DIP bits are set, read

SCSI Interrupt Status Zero

(SIST0)

,

SCSI Interrupt Status One (SIST1)

, and

DMA Status

(DSTAT)

to clear the SCSI and DMA interrupt condition and get the

interrupt status. If using 8-bit reads of the SIST0, SIST1, and DSTAT
registers to clear interrupts, insert a 12 CLK delay between the
consecutive reads to ensure that the interrupts clear properly. Both
the SCSI and DMA interrupt conditions should be handled before
leaving the interrupt service routine. It is recommended that the DMA
interrupt be serviced before the SCSI interrupt, because a serious
DMA interrupt condition could influence how the SCSI interrupt is
acted upon.

6.

When using polled interrupts, go back to Step 1 before leaving the
interrupt service routine, in case any stacked interrupts moved in
when the first interrupt was cleared. When using hardware interrupts,
the IRQ/ pin is asserted again if there are any stacked interrupts.
This should cause the system to re-enter the interrupt service
routine.

2.5.14 Chained Block Moves

Since the LSI53C875 has the capability to transfer 16-bit wide SCSI
data, a unique situation occurs when dealing with odd bytes. The
Chained Move (CHMOV) SCRIPTS instruction along with the Wide SCSI
Send (WSS) and Wide SCSI Receive (WSR) bits in the

SCSI Control

Two (SCNTL2)

register are used to facilitate these situations. The

Chained Block Move instruction is illustrated in

Figure 2.6

.

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