Avago Technologies LSI8751D - Manual (Page 153)

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DREQ Data Request Status 1
This bit indicates the status of the LSI53C875’s internal
Data Request signal (DREQ). When this bit is set, DREQ
is active. When this bit is clear, DREQ is inactive.
DACK Data Acknowledge Status 0
This bit indicates the status of the LSI53C875’s internal
Data Acknowledge signal (DACK/). When this bit is set,
DACK/ is inactive. When this bit is clear, DACK/ is active.
Register: 0x1B (0x9B)
Chip Test Three (CTEST3)
Read/Write
V[3:0] Chip revision level [7:4]
These bits identify the chip revision level for software
purposes. The value should be the same as the lower
nibble of the PCI
Revision ID register, at address 0x08 in
configuration space.
FLF Flush DMA FIFO 3
When this bit is set, data residing in the DMA FIFO is
transferred to memory, starting at the address in the
DMA
Next Address (DNAD) register. The internal DMAWR
signal, controlled by the Chip Test Five (CTEST5)
register, determines the direction of the transfer. This bit
is not self-clearing; clear it once the data is successfully
transferred by the LSI53C875. Polling of FIFO flags is
allowed during flush operations.
CLF Clear DMA FIFO 2
When this bit is set, all data pointers for the DMA FIFO
are cleared. Any data in the FIFO is lost. After the
LSI53C875 successfully clears the appropriate FIFO
pointers and registers, this bit automatically clears. This
bit does not clear the data visible at the bottom of the
FIFO.
7 4 3 2 1 0
V FLF CLF FM WRIE
x x x x 0 0 0 0