Avago Technologies LSI8751D - Manual (Page 79)

Configuration Registers 3-15
EIS Enable I/O Space 0
This bit controls the LSI53C875 response to I/O space
accesses. A value of zero disables the device response.
A value of one allows the LSI53C875 to respond to I/O
space accesses at the address specified in
Base
Address Zero (I/O) .
Register: 0x06
Status
Read/Write
The Status register records status information for PCI bus related events.
In the LSI53C875, bits 0 through 3 are reserved and bits 5, 6, 7, and 11
are not implemented by the LSI53C875.
Reads to this register behave normally. Writes are slightly different in that
bits can be cleared, but not set. A bit is reset whenever the register is
written, and the data in the corresponding bit location is a one. For
instance, to clear bit 15 and not affect any other bits, write the value
0x8000 to the register.
DPE Detected Parity Error (from Slave) 15
This bit is set by the LSI53C875 whenever it detects a
data parity error, even if parity error handling is disabled.
SSE Signaled System Error 14
This bit is set whenever a device asserts the SERR/
signal.
RMA Master Abort (from Master) 13
A master device should set this bit whenever its
transaction (except for Special Cycle) is terminated with
Master Abort. All master devices should implement this
bit.
RTA Received Target Abort (from Master) 12
A master device should set this bit whenever its
transaction is terminated by target abort. All master
devices should implement this bit.
15 14 13 12 11 10 9 8 7 5 4 3 0
DPE SSE RMA RTA R DT[1:0] DPR R NC R
0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0