Avago Technologies LSI8751D - Manual (Page 250)

7-14 Instruction Set of the I/O Processor
Timing diagrams included in this section are:
•
Target Timing
– PCI Configuration Register Read
– PCI Configuration Register Write
– Operating Register/SCRIPTS RAM Read
– Operating Register/SCRIPTS RAM Write
– External Memory Read
– External Memory Write
•
Initiator Timing
– Opcode Fetch, Nonburst
– Burst Opcode Fetch
– Back-to-Back Read
– Back-to-Back Write
– Burst Read
– Burst Write
•
External Memory Timing
– Read Cycle, Normal/Fast Memory ( 64 Kbytes), Single Byte
Access
– Write Cycle, Normal/Fast Memory ( 64 Kbytes), Single Byte
Access
– Read Cycle, Normal/Fast Memory ( 64 Kbyte), Multiple Byte
Access
– Write Cycle, Normal/Fast Memory ( 64 Kbyte), Multiple Byte
Access
– Read Cycle, Slow Memory ( 64 Kbyte)
– Write Cycle, Slow Memory ( 64 Kbyte)
– Read Cycle, Normal/Fast Memory ( 64 Kbyte)
– Write Cycle, Normal/Fast Memory ( 64 Kbyte)
– Read Cycle, Slow Memory (£ 64 Kbyte)
– Write Cycle, Slow Memory (£ 64 Kbyte)