Avago Technologies LSI8751D - Manual (Page 102)

4-10 Signal Descriptions
Table 4.4 describes the System Signals group.
Table 4.4 System Signals
Name
Pin No.
LSI53C875,
LSI53C875J,
LSI53C875N,
LSI53C875JB
Typ
e Description
CLK 145/188/A6 I Clock provides timing for all transactions on the PCI bus and is an
input to every PCI device. All other PCI signals are sampled on the
rising edge of CLK, and other timing parameters are defined with
respect to this edge. Clock can optionally serve as the SCSI core
clock, but this may effect the fast SCSI transfer rates.
RST/ 144/187/B6 I Reset forces the PCI sequencer of each device to a known state. All
T/S and S/T/S signals are forced to a high impedance state, and all
internal logic is reset. The RST/ input is synchronized internally to the
rising edge of CLK. The CLK input must be active while RST/ is active
to properly reset the device.