Avago Technologies LSI8751D - Manual (Page 253)

PCI and External Memory Interface Timing Diagrams 7-17
Figure 7.11 Operating Register/SCRIPTS RAM Read
Data
Byte Enable
Addr In
t
2
t
1
t
2
t
1
t
2
t
1
t
1
t
2
t
2
t
3
t
2
t
1
t
3
CLK
(Driven by System)
FRAME/
(Driven by Master)
AD/
(Driven by Master-Addr;
C_BE/
(Driven by Master)
PAR
(Driven by Master-Addr;
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C875)
STOP/
(Driven by LSI53C875)
DEVSEL/
(Driven by LSI53C875)
Out
t
3
In Out
t
3
LSI53C875-Data)
LSI53C875-Data
CMD
t
3