Avago Technologies LSI8751D User Manual
Page 174
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SCSI Operating Registers
•
Data Overflow – writing too many bytes to the SCSI
FIFO, or the synchronous offset causes overwriting
the SCSI FIFO.
•
Offset Underflow – the LSI53C875 is operating in
target mode and a SACK/ pulse is received when the
outstanding offset is zero.
•
Offset Overflow – the other SCSI device sends a
SREQ/ or SACK/ pulse with data which exceeds the
maximum synchronous offset defined by the
register.
•
A phase change occurs with an outstanding
synchronous offset when the LSI53C875 is operating
as an initiator.
•
Residual data in the synchronous data FIFO – a
transfer other than synchronous data receive is
started with data left in the synchronous data FIFO.
UDC
Unexpected Disconnect
2
This bit is set when the LSI53C875 is operating in the
initiator mode and the target device unexpectedly
disconnects from the SCSI bus. This bit is only valid
when the LSI53C875 operates in the initiator mode.
When the LSI53C875 operates in low level mode, any
disconnect causes an interrupt, even a valid SCSI
disconnect. This bit is also set if a selection time-out
occurs (it may occur before, at the same time, or stacked
after the STO interrupt, since this is not considered an
expected disconnect).
RST
SCSI RST/ Received
1
This bit is set when the LSI53C875 detects an active
SRST/ signal, whether the reset is generated external to
the chip or caused by the Assert SRST/ bit in the
register. The SCSI reset detection
logic is edge-sensitive, so that multiple interrupts are not
generated for a single assertion of the SRST/ signal.
PAR
Parity Error
0
This bit is set when the LSI53C875 detects a parity error
while receiving SCSI data. The Enable Parity Checking
bit (bit 3 in the
register)
must be set for this bit to become active. The LSI53C875
always generates parity when sending SCSI data.