Avago Technologies LSI8751D User Manual
Page 42
2-18
Functional Description
the DMA FIFO Byte Offset Counter, which consists of bits [1:0]
in the CTEST5 register and bits [7:0] of the DMA FIFO register.
AND the result with 0x3FF for a byte count between 0 and 536.
Step 2.
Read bit 5 in the
and
registers to determine if any bytes are left in the
register. If bit 5 is set in the
SSTAT0 or SSTAT2 register, then the least significant byte or
the most significant byte in the SODL register is full,
respectively. Checking this bit also reveals bytes left in the
SODL register from a Chained Move operation with an odd byte
count.
Step 3.
Read bit 6 in the
and
registers to determine if any bytes are left in the
SODR register. If bit 6 is set in the SSTAT0 or SSTAT2 register,
then the least significant byte or the most significant byte in the
SODR register is full, respectively.
Asynchronous SCSI Receive –
Step 1.
If the DMA FIFO size is set to 88 bytes, look at the
and
registers and calculate
if there are bytes left in the DMA FIFO. To make this calculation,
subtract the seven least significant bits of the DBC register from
the 7-bit value of the DFIFO register. AND the result with 0x7F
for a byte count between 0 and 88.
If the DMA FIFO size is set to 536 bytes (using bit 5 of the
register), subtract the 10 least significant
bits of the
register from the 10-bit
value of the DMA FIFO Byte Offset Counter, which consists of
bits [1:0] in the CTEST5 register and bits [7:0] of the DMA FIFO
register. AND the result with 0x3FF for a byte count between
0 and 536.
Step 2.
Read bit 7 in the
and
register to determine if any bytes are left in the
register. If bit 7 is set in the
SSTAT0 or SSTAT2, then the least significant byte or the most
significant byte is full, respectively.