Avago Technologies LSI8751D User Manual
Page 71
PCI Cache Mode
3-7
2.
The
register contains a legal burst size (2, 4, 8, 16,
32, 64, or 128) value and that value must be less than or equal to
the
burst size.
3.
The chip has enough bytes in the DMA FIFO to complete at least
one full cache line burst.
4.
The chip is aligned to a cache line boundary.
When these conditions are met, the LSI53C875 issues a Write and
Invalidate command instead of a Memory Write command during all PCI
write cycles.
Multiple Cache Line Transfers – The Write and Invalidate command
can write multiple cache lines of data in a single bus ownership. The chip
issues a burst transfer as soon as it reaches a cache line boundary. The
size of the transfer is not automatically the cache line size, but rather a
multiple of the cache line size specified in the Revision 2.1 of the PCI
specification. The logic selects the largest multiple of the cache line size
based on the amount of data to transfer, with the maximum allowable
burst size being that determined from the
burst
size bits and
, bit 2. If multiple cache line size
transfers are not desired, set the
burst size to
exactly the cache line size and the chip only issues single cache line
transfers.
After each data transfer, the chip re-evaluates the burst size based on
the amount of remaining data to transfer and again selects the highest
possible multiple of the cache line size, no larger than the
burst size. The most likely scenario of this scheme is that the
chip selects the
burst size after alignment, and
issues bursts of this size. The burst size is, in effect, throttled down
toward the end of a long Memory Move or Block Move transfer until only
the cache line size burst size is left. The chip finishes the transfer with
this burst size.
3.2.5.1 Latency
In accordance with the PCI specification, the latency timer is ignored
when issuing a Write and Invalidate command such that when a latency
time-out occurs, the LSI53C875 continues to transfer up to a cache line
boundary. At that point, the chip relinquishes the bus, and finishes the