Avago Technologies LSI8751D - Manual (Page 291)

SCSI Timing Diagrams 7-55
Table 7.26 SCSI-2 Fast Transfers 10.0 Mbytes/s (8-Bit Transfers) or 20.0 Mbytes/s
(16-Bit Transfers), 40 MHz Clock
Symbol Parameter Min Max Unit
t
1
Send SREQ/ or SACK/ assertion pulse width 35 – ns
t
2
Send SREQ/ or SACK/ deassertion pulse width 35 – ns
t
1
Receive SREQ/ or SACK/ assertion pulse width 20 – ns
t
2
Receive SREQ/ or SACK/ deassertion pulse width 20 – ns
t
3
Send data setup to SREQ/ or SACK/ asserted 33 – ns
t
4
Send data hold from SREQ/ or SACK/ asserted 40 – ns
t
5
Receive data setup to SREQ/ or SACK/ asserted 0 – ns
t
6
Receive data hold from SREQ/ or SACK/ asserted 10 – ns
Table 7.27 SCSI-2 Fast Transfers 10.0 Mbytes/s (8-Bit Transfers) or 20.0 Mbytes/s
(16-Bit Transfers), 50 MHz Clock
Symbol Parameter Min Max Unit
t
1
Send SREQ/ or SACK/ assertion pulse width 35 – ns
t
2
Send SREQ/ or SACK/ deassertion pulse width 35 – ns
t
1
Receive SREQ/ or SACK/ assertion pulse width 20 – ns
t
2
Receive SREQ/ or SACK/ deassertion pulse width 20 – ns
t
3
Send data setup to SREQ/ or SACK/ asserted 33 – ns
t
4
Send data hold from SREQ/ or SACK/ asserted 40
1
1. Analysis of system configuration is recommended due to reduced driver skew margin in differential
systems.
Notes: Transfer period bits (bits [7:5] in the SCSI Transfer (SXFER) register) are set to zero and the
Extra Clock Cycle of Data Setup bit (bit 7 in SCSI Control One (SCNTL1) ) is set. For Fast SCSI,
set the TolerANT Enable bit (bit 7 in SCSI Test Three (STEST3) ).
– ns
t
5
Receive data setup to SREQ/ or SACK/ asserted 0 – ns
t
6
Receive data hold from SREQ/ or SACK/ asserted 10 – ns