Avago Technologies LSI8751D - Manual (Page 256)

7-20 Instruction Set of the I/O Processor
Figure 7.13 External Memory Read
t
12
CLK
(Driven by System)
PAR
(Driven by Master-Addr;
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C875)
STOP/
(Driven by LSI53C875)
DEVSEL/
(Driven by LSI53C875)
AD
(Driven by Master-Addr;
C_BE/
(Driven by Master)
FRAME/
(Driven by Master)
Data Driven by Memory)
1 2 3 4 5 6 7 8 9 10
LSI53C875-Data)
LSI53C875-Data)
MAD
(Addr Drvn by LSI53C875;
High Order
Address
Middle Order
Address
Low Order
Address
MAS1/
(Driven by LSI53C875)
MAS0/
(Driven by LSI53C875)
MCE/
(Driven by LSI53C875)
MOE/
(Driven by LSI53C875)
MWE/
(Driven by LSI53C875)
t
1
CMD
t
3
t
11
t
15
t
2
t
1
t
2
Addr
In
t
1
t
2
t
1
t
2
t
1
t
13
Byte Enable
GPIO_MAS2/
(Driven by LSI53C875)