Avago Technologies LSI8751D - Manual (Page 234)

6-38 Instruction Set of the I/O Processor
6.7.1 First Dword
IT[2:0] Instruction Type [31:29]
These bits should be 111, indicating the Load and Store
instruction.
DSA DSA Relative 28
When this bit is cleared, the value in the DMA SCRIPTS
Pointer Save (DSPS) is the actual 32-bit memory address
used to perform the Load and Store to/from. When this
bit is set, the chip determines the memory address to per-
form the Load and Store to/from by adding the 24-bit
signed offset value in the
DMA SCRIPTS Pointer Save
(DSPS) to the Data Structure Address (DSA) .
R Reserved [27:26]
NF No Flush (Store instruction only) 25
When this bit is set, the LSI53C875 performs a Store
without flushing the prefetch unit. When this bit is cleared,
the Store instruction automatically flushes the prefetch
unit. Use No Flush if the source and destination are not
within four instructions of the current Store instruction.
This bit has no effect on the Load instruction.
Note: This bit has no effect unless the Prefetch Enable bit in the
DMA Control (DCNTL) register is set. For information on
SCRIPTS instruction prefetching, see Chapter 2, “Func-
tional Description.”
LS Load/Store 24
When this bit is set, the instruction is a Load. When
cleared, it is a Store.
Bit Source Destination
SIOM (Load) Memory Register
DIOM (Store) Register Memory