Avago Technologies LSI8751D - Manual (Page 36)

2-12 Functional Description
Software drivers for the LSI53C875 should access registers by their
logical name (that is, SCNTL0) rather than by their address. The logical
name should be equated to the register’s big endian address in big
endian mode (SCNTL0 = 0x03), and its little endian address in little
endian mode (SCNTL0 = 0x00). This way, there is no change to the
software when moving from one mode to the other; only the equate
statement setting the operating modes needs to be changed.
Addressing of registers from within a SCRIPTS instruction is independent
of bus mode. Internally, the LSI53C875 always operates in little endian
mode.
2.5.6 Loopback Mode
The LSI53C875 loopback mode allows testing of both initiator and target
functions and, in effect, lets the chip communicate with itself. When the
Loopback Enable bit is set in the
SCSI Test One (STEST1) register, the
LSI53C875 allows control of all SCSI signals whether the chip is
operating in initiator or target mode. For more information on this mode
of operation refer to the SCSI SCRIPTS Processors Programming Guide.
2.5.7 Parity Options
The LSI53C875 implements a flexible parity scheme that allows control
of the parity sense, allows parity checking to be turned on or off, and has
the ability to deliberately send a byte with bad parity over the SCSI bus
to test parity error recovery procedures.
Table 2.2 defines the bits that
are involved in parity control and observation. Table 2.3 describes the
parity control function of the Enable Parity Checking and Assert SCSI
Even Parity bits in the
SCSI Control Zero (SCNTL0) register. Table 2.4
describes the options available when a parity error occurs.
The LSI53C875N has four additional parity pins for checking incoming
data on the PCI bus. These pins are assigned to each byte of the PCI
address/data bus, and work in addition to the PAR (PCI parity) pin. In
PCI master read or slave write operations, each byte of incoming data
on the PCI bus is checked against its corresponding parity line, in
addition to the normal parity checking against the PCI PAR signal. In PCI
master write or slave read operations, parity is generated for each byte.
This extra parity checking is always enabled for the LSI53C875N. The
host system must support these pins. This feature is not register
selectable. A parity error on any Byte Parity pin for PCI master read or