Avago Technologies LSI8751D User Manual
Page 121
5-5
time-out occurs while attempting to select a target device,
SATN/ is deasserted at the same time SSEL/ is
deasserted. When this bit is cleared, the SATN/ signal is
not asserted during selection. When executing SCSI
SCRIPTS, this bit is controlled by the SCRIPTS
processor, but manual setting is possible in low level
mode.
EPC
Enable Parity Checking
3
When this bit is set, the SCSI data bus is checked for odd
parity when data is received from the SCSI bus in either
initiator or target mode. Parity is also checked as data
goes from the SCSI FIFO to the DMA FIFO. If a parity
error is detected, bit 0 of the
register is set and an interrupt may be
generated.
If the LSI53C875 is operating in the initiator mode and a
parity error is detected, assertion of SATN/ is optional,
but the transfer continues until the target changes phase.
When this bit is cleared, parity errors are not reported.
When these bits are set in the LSI53C875N, the chip
again checks inbound SCSI parity at the SCSI FIFO–
DMA FIFO interface after the data has passed through
the SCSI FIFO. The parity bits are not passed through
the DMA FIFO, but parity is generated before the data is
sent out on the PCI bus.
R
Reserved
2
AAP
Assert SATN/ on Parity Error
1
When this bit is set, the LSI53C875 automatically asserts
the SATN/ signal upon detection of a parity error. SATN/
is only asserted in the initiator mode. The SATN/ signal
is asserted before deasserting SACK/ during the byte
transfer with the parity error. Also set the Enable Parity
Checking bit for the LSI53C875 to assert SATN/ in this
manner. A parity error is detected on data received from
the SCSI bus.
If the Assert SATN/ on Parity Error bit is cleared or the
Enable Parity Checking bit is cleared, SATN/ is not
automatically asserted on the SCSI bus when a parity
error is received.