Avago Technologies LSI8751D - Manual (Page 152)

5-36 SCSI Operating Registers
SIGP Signal Process 6
This bit is a copy of the SIGP bit in the Interrupt Status
(ISTAT) register (bit 5). The SIGP bit is used to signal a
running SCRIPTS instruction. When this register is read,
the SIGP bit in the
Interrupt Status (ISTAT) register is
cleared.
CIO Configured as I/O 5
This bit is defined as the Configuration I/O Enable Status
bit. This read only bit indicates if the chip is currently
enabled as I/O space. Both bits 4 and 5 are set if the chip
is dual-mapped.
CM Configured as Memory 4
This bit is defined as the configuration memory enable
status bit. This read only bit indicates if the chip is
currently enabled as memory space. Both bits 4 and 5
are set if the chip is dual-mapped.
SRTCH SCRATCHA/B Operation 3
This bit controls the operation of the Scratch Register A
(SCRATCHA) and Scratch Register B (SCRATCHB)
registers. When it is set, SCRATCHB contains the RAM
base address value from the PCI configuration RAM
Base Address register. This is the base address for the
4 Kbyte internal RAM. In addition, the
Scratch Register A
(SCRATCHA) register displays the memory mapped
based address of the chip operating registers. When this
bit is cleared, the
Scratch Register A (SCRATCHA) and
Scratch Register B (SCRATCHB) registers return to
normal operation.
Note: Bit 3 is the only writable bit in this register. All other bits are
read only. When modifying this register, all other bits must
be written to zero. Do not execute a read-modify-write to
this register.
TEOP SCSI True End of Process 2
This bit indicates the status of the LSI53C875’s internal
TEOP signal. The TEOP signal acknowledges the
completion of a transfer through the SCSI portion of the
LSI53C875. When this bit is set, TEOP is active. When
this bit is clear, TEOP is inactive.