Avago Technologies LSI8751D - Manual (Page 304)

B-4 External Memory Interface Diagram Examples
Figure B.4 512 Kbyte Interface with 150 ns Memory
LSI53C875
MOE/
8
MAD[7:0]
Bus
8
A[7:0]
8
A[15:8]
8
V
SS
MAS0/
MAS1/
8
Note: MAD bus sense logic enabled for 512 Kbytes of slow memory (150 ns devices, additional time required for
HCT139 @ 33 MHz). The HCT374s may be replaced with HCT377s.
GPIO4
MWE/
V
PP
Control
+ 12 V
V
PP
Optional - for Flash Memory only, not
required for EEPROMS.
D[7:0] MAD0 4.7 K
3
MAD2 4.7 K
OE
D0
A0
A16
OE
D0
A0
A16
OE
D0
A0
A16
OE
D0
A0
A16
A
B
GB
Y0
Y1
Y2
Y3
MCE/
HCT139
CE CE CE CE
27C010-15/28F010-15 Sockets
D0
D7
Q0
Q7
HCT374
CK 0E
D0
D7
Q0
Q7
HCT374
CK 0E
D0
D2
Q0
Q2
HCT377
CK 0E
MAD[2:0] Bus
A16
D7 D7 D7 D7
A17
A18