Avago Technologies LSI8751D - Manual (Page 248)

7-12 Instruction Set of the I/O Processor
Table 7.17 and Figure 7.7 provide Reset Input timing data.
Figure 7.7 Reset Input
Table 7.17 Reset Input
Symbol Parameter Min Max Unit
t
1
Reset pulse width 10 – t
CLK
t
2
Reset deasserted setup to CLK HIGH 0 – ns
t
3
MAD setup time to CLK HIGH
(for configuring the MAD bus only) 20 – ns
t
4
MAD hold time from CLK HIGH
(for configuring the MAD bus only) 20 – ns
t
2
1. When enabled.
CLK
RST/
MAD
1 Valid Data
t
3
t
4
t
1