Avago Technologies LSI8751D - Manual (Page 229)

Memory Move Instructions 6-33
DCV Data Compare Value [7:0]
This 8-bit field is the data to be compared against the
register. These bits are used in conjunction with the Data
Compare Mask Field to test for a particular data value.
6.5.2 Second Dword
Jump Address [31:0]
This 32-bit field contains the address of the next
instruction to fetch when a jump is taken. Once the
LSI53C875 fetches the instruction from the address
pointed to by these 32 bits, this address is incremented
by 4, loaded into the
DMA SCRIPTS Pointer (DSP)
register and becomes the current instruction pointer.
6.6 Memory Move Instructions
For Memory Move instructions, bits 5 and 4 (SIOM and DIOM) in the
DMA Mode (DMODE) register determine whether the source or
destination addresses reside in memory or I/O space. By setting these
bits appropriately, data may be moved within memory space, within I/O
space, or between the two address spaces.
The Memory Move instruction is used to copy the specified number of
bytes from the source address to the destination address.
Allowing the LSI53C875 to perform memory moves frees the system
processor for other tasks and moves data at higher speeds than
available from current DMA controllers. Up to 16 Mbytes may be
transferred with one instruction. There are two restrictions:
•
Both the source and destination addresses must start with the same
address alignment A[1:0]. If the source and destination are not
aligned, then an illegal instruction interrupt occurs. For the PCI
Cache Line Size register setting to take effect, the source and
destination must be the same distance from a cache line boundary.
•
Indirect addresses are not allowed. A burst of data is fetched from
the source address, put into the DMA FIFO and then written out to
the destination address. The move continues until the byte count
decrements to zero, then another SCRIPTS is fetched from system
memory.