Avago Technologies LSI8751D - Manual (Page 262)

7-26 Instruction Set of the I/O Processor
Figure 7.17 Back-to-Back Read
t
1
CLK
GPIO0_FETCH/
GPIO1_MASTER/
REQ/
GNT/
FRAME/
C_BE/
PAR/
(Driven by System)
(Driven by LSI53C875)
(Driven by LSI53C875)
(Driven by LSI53C875)
(Driven by Arbiter)
(Driven by LSI53C875)
AD/
Target-Data)
(Driven by LSI53C875)
IRDY/
(Driven by Target)
(Driven by
LSI53C875-Addr;
Target-Data)
TRDY/
STOP/
DEVSEL/
(Driven by LSI53C875)
(Driven by Target)
(Driven by Target)
(Driven by
t
9
t
10
t
6
t
4
t
5
t
3
Data In
t
3
t
1
t
3 t
1
t
3
t
2
t
2
t
2
t
1
LSI53C875-Addr;
Addr Out Data In
Addr Out
t
2
CMD BE CMD BE
Out In Out In