Avago Technologies LSI8751D - Manual (Page 269)

PCI and External Memory Interface Timing Diagrams 7-33
Figure 7.21 Read Cycle, Normal/Fast Memory (
≥
64 Kbytes), Single Byte Access
(Cont.)
t
17
CLK
MAD
(Addr driven by LSI53C875 ;
Data driven by memory)
MAS2/
(Driven by LSI53C875)
MAS1/
(Driven by LSI53C875)
MCE/
(Driven by LSI53C875)
MOE/
(Driven by LSI53C875)
MWE/
(Driven by LSI53C875)
10 11 12 13 14 15 16 17 18
MAS0/
(Driven by LSI53C875)
t
15f
t
14f
t
16f
19
Valid
Read Data
t
18
t
19