Avago Technologies LSI8751D - Manual (Page 76)

3-12 PCI Functional Description
Table 3.2 PCI Configuration Register Map
31 16 15 0
Device ID Vendor ID 0x00
Status Command 0x04
Class Code Revision ID 0x08
Not Supported Header Type Latency Timer Cache Line Size 0x0C
Base Address Zero (I/O)
1
1. I/O Base is supported.
0x10
Base Address One (Memory)
2
2. Memory Base is supported.
0x14
Base Address Two (Memory) SCRIPTS RAM
3
3. This register powers up enabled and can be disabled by pull-down resistors on the MAD5 pin.
0x18
Not Supported 0x1C
Not Supported 0x20
Not Supported 0x24
Reserved 0x28
Subsystem ID (SSID) Subsystem Vendor ID (SSVID) 0x2C
Expansion ROM Base Address
4
4. If expansion memory is enabled through pull-down resistors on the MAD[7:0] bus.
Note: Addresses 0x40–0x7F are not defined for the LSI53C875. Addresses 0x48–0x7F are not defined
for the LSI53C875E. All unsupported registers are not writable and return all zeros when read.
Reserved registers also return zeros when read.
0x30
Reserved Capabilities Pointer 0x34
Reserved 0x38
Max_Lat Min_Gnt Interrupt Pin Interrupt Line 0x3C
Power Management Capabilities Next Item Pointer Capability ID 0x40
Data
Bridge Support Exten-
sions (PMCSR_BSE)
Power Management Control/Status 0x44