Avago Technologies LSI8751D User Manual
Page 154
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SCSI Operating Registers
FM
Fetch Pin Mode
1
When set, this bit causes the FETCH/ pin to deassert
during indirect and table indirect read operations.
FETCH/ is only active during the opcode portion of an
instruction fetch. This allows the storage of SCRIPTS in
a PROM while data tables are stored in RAM.
If this bit is not set, FETCH/ is asserted for all bus cycles
during instruction fetches.
WRIE
Write and Invalidate Enable
0
This bit, when set, causes the issuing of Memory Write
and Invalidate commands on the PCI bus whenever legal.
These conditions are described in detail in
Registers: 0x1C–0x1F (0x9C–0x9F)
Temporary (TEMP)
Read/Write
TEMP
Temporary
[31:0]
This 32-bit register stores the Return instruction address
pointer from the Call instruction. The address pointer
stored in this register is loaded into the
register when a Return instruction is
executed. This address points to the next instruction to
execute. Do not write to this register while the LSI53C875
is executing SCRIPTS.
During any Memory-to-Memory Move operation, the
contents of this register are preserved. The power-up
value of this register is indeterminate.
31
0
TEMP
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x