Avago Technologies LSI8751D - Manual (Page 197)

LSI53C875/875E PCI to Ultra SCSI I/O Processor 6-1
Chapter 6
Instruction Set of the
I/O Processor
After power-up and initialization, the LSI53C875 can be operated in the
low level register interface mode or in the high level SCSI SCRIPTS
mode.
Chapter 6 is divided into the following sections:
•
Section 6.1, “SCSI SCRIPTS”
•
Section 6.2, “Block Move Instructions”
•
Section 6.3, “I/O Instruction”
•
Section 6.4, “Read/Write Instructions”
•
Section 6.5, “Transfer Control Instructions”
•
Section 6.6, “Memory Move Instructions”
•
Section 6.7, “Load and Store Instructions”
With the low level register interface mode, the user has access to the
DMA control logic and the SCSI bus control logic. An external processor
has access to the SCSI bus signals and the low level DMA signals, which
allows creation of complicated board level test algorithms. The low level
interface is useful for backward compatibility with SCSI devices that
require certain unique timings or bus sequences to operate properly.
Another feature allowed at the low level is loopback testing. In loopback
mode, the SCSI core can be directed to talk to the DMA core to test
internal data paths all the way out to the chip’s pins.
6.1 SCSI SCRIPTS
To operate in the SCSI SCRIPTS mode, the LSI53C875 requires only a
SCRIPTS start address. The start address must be at a longword (four
byte) boundary. This aligns subsequent SCRIPTS at a longword