Avago Technologies LSI53C896 - Manual (Page 97)

PCI Bus Interface Signals 3-9
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
3.2.5 Error Reporting Signals
Table 3.6 describes the signals for the Error Reporting Signals group.
Table 3.6 Error Reporting Signals
Name Bump Type Strength Description
PERR/ R4 S/T/S 16 mA
PCI
Parity Error may be pulsed active by an agent that detects
a data parity error. PERR/ can be used by any agent to signal
data corruption. However, on detection of a PERR/ pulse, the
central resource may generate a nonmaskable interrupt to
the host CPU, which often implies the system is unable to
continue operation when error processing is complete.
SERR/ R3 O 16 mA
PCI
System Error is an open drain output that reports address
parity errors as well as critical errors other than parity.