Scripts fetch selector (sfs), Memory move write selector (mmws), Registers: 0xa4–0xa7 – Avago Technologies LSI53C896 User Manual
Page 220: Registers: 0xa8–0xab
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Registers
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Writes to the MMRS register are unaffected. Clearing the
PCI Configuration Info Enable bit causes the MMRS
register to return to normal operation.
Registers: 0xA4–0xA7
Memory Move Write Selector (MMWS)
Read/Write
MMWS
Memory Move Write Selector
[31:0]
Supplies AD[63:32] during data write operations during
Memory-to-Memory Moves and absolute address
STORE operations.
A special mode of this register can be enabled by setting
the PCI Configuration Info Enable bit in the
register. If this bit is set, the
MMWS register returns bits [63:32] of the SCRIPTS RAM
PCI
Base Address Register Two (SCRIPTS RAM)
in bits
[31:0] of the MMWS register when read.
Writes to the MMWS register are unaffected. Clearing the
PCI Configuration Info Enable bit causes the MMWS
register to return to normal operation.
Registers: 0xA8–0xAB
SCRIPTS Fetch Selector (SFS)
Read/Write
SFS
SCRIPTS Fetch Selector
[31:0]
Supplies AD[63:32] during SCRIPTS fetches and Indirect
fetches (excluding Table Indirect fetches). This register can
be loaded automatically using a 64-bit jump instruction.
A special mode of this register can be enabled by setting
the PCI Configuration Info Enable bit in the
register. If this bit is set, bits
31
0
MMWS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
31
0
SFS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0