Avago Technologies LSI53C896 - Manual (Page 16)

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Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
6.1 Absolute Maximum Stress Ratings 6-2
6.2 Operating Conditions 6-2
6.3 LVD Driver SCSI Signals – SD[15:0], SDP[1:0], SREQ/,
SREQ2/, SACK/, SACK2/, SMSG/, SIO/, SCD/, SATN/,
SBSY/, SSEL/, SRST/
6-3
6.4 LVD Receiver SCSI Signals – SD[15:0], SDP[1:0], SREQ/,
SREQ2/, SACK/, SACK2/, SMSG/, SIO/, SCD/, SATN/,
SBSY/, SSEL/, SRST/
6-3
6.5 A and B DIFFSENS SCSI Signals 6-4
6.6 Input Capacitance 6-4
6.7 Bidirectional Signals – GPIO0_FETCH/, GPIO1_MASTER/,
GPIO2, GPIO3, GPIO4, MAD[7:0]
1
6-5
6.8 Output Signals – MAS/[1:0], MCE/, MOE/_TESTOUT
1
,
MWE/, TDO 6-5
6.9 Bidirectional Signals – AD[63:0], C_BE[7:0]/, FRAME/,
IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR, PAR64,
REQ64/, ACK64/
6-6
6.10 Input Signals – CLK, GNT/, IDSEL, INT_DIR, RST/,
SCLK, TCK, TDI, TEST_HSC, TEST_RST/, TMS
6-6
6.11 Output Signals – INTA, INTB, ALT_INTA, ALT_INTB,
REQ/
6-7
6.12 Output Signal – SERR/ 6-7
6.13 TolerANT Technology Electrical Characteristics
for SE SCSI Signals
6-8
6.14 External Clock 6-12
6.15 Reset Input 6-13
6.16 Interrupt Output 6-14
6.17 PCI Configuration Register Read 6-16
6.18 PCI Configuration Register Write 6-17
6.19 Operating Register/SCRIPTS RAM Read, 32-Bit 6-18
6.20 Operating Register/SCRIPTS RAM Read, 64-Bit 6-19
6.21 Operating Register/SCRIPTS RAM Write, 32-Bit 6-20
6.22 Operating Register/SCRIPTS RAM Write, 64-Bit 6-21
6.23 Nonburst Opcode Fetch, 32-Bit Address and Data 6-22
6.24 Burst Opcode Fetch, 32-Bit Address and Data 6-24
6.25 Back to Back Read, 32-Bit Address and Data 6-26
6.26 Back to Back Write, 32-Bit Address and Data 6-28
6.27 Burst Read, 32-Bit Address and Data 6-30
6.28 Burst Read, 64-Bit Address and Data 6-32