Avago Technologies LSI53C896 - Manual (Page 95)

PCI Bus Interface Signals 3-7
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
3.2.3 Interface Control Signals
Table 3.4 describes the signals for the Interface Control Signals group.
PAR64 AA5 T/S 16 mA
PCI
Parity64 is the even parity bit that
protects the AD[63:32] and C_BE[7:4]/
lines. During address phase, both the
address and command bits are covered.
During data phase, both data and byte
enables are covered.
Table 3.3 Address and Data Signals (Cont.)
Name Bump Type Strength Description
Table 3.4 Interface Control Signals
Name Bump Type Strength Description
ACK64/ AB1 S/T/S 16 mA
PCI
Acknowledge 64-bit transfer is driven by the current bus
target to indicate its ability to transfer 64-bit data.
REQ64/ AA2 S/T/S 16 mA
PCI
Request 64-bit transfer is driven by the current bus master
to indicate a request to transfer 64-bit data.
FRAME/ P2 S/T/S 16 mA
PCI
Cycle Frame is driven by the current master to indicate the
beginning and duration of an access. FRAME/ is asserted
to indicate that a bus transaction is beginning. While
FRAME/ is deasserted, either the transaction is in the final
data phase or the bus is idle.
TRDY/ P3 S/T/S 16 mA
PCI
Target Ready indicates the target agent’s (selected
device’s) ability to complete the current data phase of the
transaction. TRDY/ is used with IRDY/. A data phase is
completed on any clock when used with IRDY/. A data
phase is completed on any clock when both TRDY/ and
IRDY/ are sampled asserted. During a read, TRDY/
indicates that valid data is present on AD[31:0]. During a
write, it indicates that the target is prepared to accept data.
Wait cycles are inserted until both IRDY/ and TRDY/ are
asserted together.
IRDY/ N4 S/T/S 16 mA
PCI
Initiator Ready indicates the initiating agent’s (bus
master’s) ability to complete the current data phase of the
transaction. IRDY/ is used with TRDY/. A data phase is
completed on any clock when both IRDY/ and TRDY/ are
sampled asserted. During a write, IRDY/ indicates that valid
data is present on AD[31:0]. During a read, it indicates that
the master is prepared to accept data. Wait cycles are
inserted until both IRDY/ and TRDY/ are asserted together.