Expansion rom base address – Avago Technologies LSI53C896 User Manual

Page 125

PCI Configuration Registers

4-13

Version 3.3

Registers: 0x30–0x33

Expansion ROM Base Address
Read/Write

ERBA

Expansion ROM Base Address

[31:0]

This four-byte register handles the base address and size
information for the expansion ROM. It functions exactly
like the

Base Address Register Zero (I/O)

and

Base Address Register One (MEMORY)

registers, except

that the encoding of the bits is different. The upper 21 bits
correspond to the upper 21 bits of the expansion ROM
base address.

The expansion ROM Enable bit, bit 0, is the only bit
defined in this register. This bit controls whether or not
the device accepts accesses to its expansion ROM.
When the bit is set, address decoding is enabled, and a
device is used with or without an expansion ROM
depending on the system configuration. To access the
external memory interface, also set the Memory Space
bit in the

Command

The host system detects the size of the external memory
by first writing the

Expansion ROM Base Address

with all ones and then reading back the register. The
SCSI functions of the LSI53C896 respond with zeros in
all don’t care locations. The ones in the remaining bits
represent the binary version of the external memory size.
For example, to indicate an external memory size of
32 Kbytes, this register, when written with ones and read
back, returns ones in the upper 17 bits.

The size of the external memory is set through MAD[3:1].
Refer to

Section 3.7, “MAD Bus Programming,”

for the

possible size encodings available.

ERBA