Avago Technologies LSI53C896 - Manual (Page 59)

SCSI Functional Description 2-31
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
2.2.12 DMA FIFO
The DMA FIFO is 8 bytes wide by 118 transfers deep. The DMA FIFO
is illustrated in
Figure 2.3 . The default DMA FIFO size is 112 bytes to
assure compatibility with older products in the LSI53C8XX family.
The DMA FIFO size may be set to 944 bytes by setting the DMA FIFO
Size bit, bit 5, in the
Chip Test Five (CTEST5) register.
Figure 2.3 DMA FIFO Sections
The LSI53C896 supports 64-bit memory and automatically supports
misaligned DMA transfers. A 944-byte FIFO allows the LSI53C896 to
support 2, 4, 8, 16, 32, 64, or 128 Dword bursts across the PCI
bus interface.
8 Bytes Wide
Byte Lane 7 Byte Lane 6 Byte Lane 5 Byte Lane 4 Byte Lane 3 Byte Lane 2 Byte Lane 1 Byte Lane 0
118
Transfers
Deep