Avago Technologies LSI53C896 User Manual
Page 37
PCI Functional Description
2-9
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Read Multiple with Read Line Enabled – When both the Read
Multiple and Read Line modes are enabled, the Read Line command is
not issued if these conditions are met. Instead, a Read Multiple
command is issued, even though the conditions for Read Line are met.
If the Read Multiple mode is enabled and the Read Line mode is
disabled, Read Multiple commands are issued if the Read Multiple
conditions are met.
2.1.2.13 Memory Write and Invalidate Command
The Memory Write and Invalidate command is identical to the
Memory Write command, except that it additionally guarantees a minimum
transfer of one complete cache line. That is, the master intends to write
all bytes within the addressed cache line in a single PCI transaction unless
interrupted by the target. This command requires implementation of the
PCI
register at address 0x0C in PCI configuration space.
The LSI53C896 enables Memory Write and Invalidate cycles when bit 0
(WRIE) in the
register and bit 4 (WIE) in the
PCI
register are set. When the following conditions are met,
Memory Write and Invalidate commands are issued:
•
The Cache Line Size Enable (CLSE) bit, bit 7 of the
register), Write and Invalidate Enable (WRIE)
bit, bit 0, of the
register), and PCI
configuration
register, bit 4 are set.
•
The
register for each function contains a legal burst
size value in Dwords (2, 4, 8, 16, 32, 64, or 128), and that value is
less than or equal to the
burst size.
•
The chip has enough bytes in the DMA FIFO to complete at least
one full cache line burst.
•
The chip is aligned to a cache line boundary.
When these conditions are met, the LSI53C896 issues a Write and
Invalidate command instead of a Memory Write command during all PCI
write cycles.
Multiple Cache Line Transfers – The Memory Write and Invalidate
command can write multiple cache lines of data in a single bus
ownership. The chip issues a burst transfer as soon as it reaches a
cache line boundary. The size of the transfer is not automatically the