Chip test four (ctest4), Register: 0x21 – Avago Technologies LSI53C896 User Manual
Page 173
SCSI Registers
4-61
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Step 1.Subtract the seven least significant bits of the
register from the
seven bit value of the DFBOC which is made up
of the
register (bits [6:0]).
Step 2.AND the result with 0x7F for a byte count between
zero and 112.
Note:
To calculate the total number of bytes in both the DMA
FIFO and SCSI Logic, refer to
in
Chapter 2, “Functional Description.”
Register: 0x21
Chip Test Four (CTEST4)
Read/Write
BDIS
Burst Disable
7
When set, this bit causes the LSI53C896 SCSI function
to perform back to back cycles for all transfers. When this
bit is cleared, back to back transfers for opcode fetches
and burst transfers for data moves are performed.
FBL3
FIFO Byte Control
6
This bit is used with FBL[2:0]. Refer to Bits [2:0]
description in this register.
ZSD
SCSI Data High Impedance
5
Setting this bit causes the LSI53C896 SCSI function to
place the SCSI data bus SD[15:0] and the parity lines
SDP[1:0] in a high impedance state. To transfer data on
the SCSI bus, clear this bit.
SRTM
Shadow Register Test Mode
4
Setting this bit allows access to the shadow registers
used by Memory-to-Memory Move operations. When this
bit is set, register accesses to the
and
registers are directed to
the shadow copies STEMP (Shadow TEMP) and SDSA
(Shadow DSA). The registers are shadowed to prevent
them from being overwritten during a Memory-to-Memory
7
6
5
4
3
2
0
BDIS
FBL3
ZSD
SRTM
MPEE
FBL[2:0]
0
0
0
0
0
0
0
0