Avago Technologies LSI53C896 User Manual
Page 249
I/O Instructions
5-21
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Table Relative
Treats the alternate jump address as a relative jump and
fetches the device ID, synchronous offset, and
synchronous period indirectly. The value in bits [23:0] of
the first four bytes of the SCRIPTS instruction is added to
the data structure base address to form the fetch address.
Sel
Select with ATN/
24
This bit specifies whether SATN/ is asserted during the
selection phase when the LSI53C896 is executing a Select
instruction. When operating in the initiator mode, set this
bit for the Select instruction. If this bit is set on any other
I/O instruction, an illegal instruction interrupt is generated.
R
Reserved
[23:20]
ENDID[3:0]
Encoded SCSI Destination ID
[19:16]
This 4-bit field specifies the destination SCSI ID for an I/O
instruction.
R
Reserved
[15:11]
CA
Set/Clear Carry
10
This bit is used in conjunction with a Set or Clear
instruction to set or clear the Carry bit. Setting this bit
with a Set instruction asserts the Carry bit in the ALU.
Clearing this bit with a Clear instruction deasserts the
Carry bit in the ALU.
TM
Set/Clear Target Mode
9
This bit is used in conjunction with a Set or Clear
instruction to set or clear the target mode. Setting this bit
with a Set instruction configures the LSI53C896 as a target
device (this sets bit 0 of the
register). Clearing this bit with a Clear instruction
configures the LSI53C896 as an initiator device (this clears
bit 0 of the SCNTL0 register).
Command
Table Offset
Absolute Jump Offset