Avago Technologies LSI53C896 - Manual (Page 41)

PCI Functional Description 2-13
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
smaller than the burst length, all bytes for that transfer are read in one
PCI burst transaction. If the transfer crosses a Dword boundary
(A[1:0] = 0b00), a Memory Read Line command is issued. When the
transfer crosses a cache boundary (depends on the cache line size
programmed into the PCI configuration register), a Memory Read
Multiple command is issued. If a transfer does not cross a Dword or
cache boundary, or if cache mode is not enabled, a Memory Read
command is issued.
2.1.4.4 Memory Write Caching
Writes are aligned in a single burst transfer to get to a cache boundary.
At that point, Memory Write and Invalidate commands are issued and
continue at the burst length programmed into the
DMA Mode (DMODE)
register. Memory Write and Invalidate commands are issued as long as
the remaining byte count is greater than the Memory Write and Invalidate
threshold. When the byte count goes below this threshold, a single
Memory Write burst is issued to complete the transfer. The general
pattern for PCI writes is:
•
A single Memory Write to align to a cache boundary.
•
Multiple Memory Write and Invalidates.
•
A single data residual Memory Write to complete the transfer.
Table 2.2 describes PCI cache mode alignment.