Scsi status two (sstat2), Register: 0x0f – Avago Technologies LSI53C896 User Manual
Page 160
4-48
Registers
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Register:
0x0F
SCSI Status Two (SSTAT2)
Read Only
ILF
SIDL Most Significant Byte Full
7
This bit is set when the most significant byte in the
contains data. Data is
transferred from the SCSI bus to the SCSI Input Data
Latch register before being sent to the DMA FIFO and
then to the host bus. The SIDL register contains SCSI
data received asynchronously. Synchronous data
received does not flow through this register.
ORF1
SODR Most Significant Byte Full
6
This bit is set when the most significant byte in the SCSI
Output Data Register (SODR, a hidden buffer register
which is not accessible) contains data. The SODR
register is used by the SCSI logic as a second storage
register when sending data synchronously. It is not
accessible to the user. This bit determines how many
bytes reside in the chip when an error occurs.
OLF1
SODL Most Significant Byte Full
5
This bit is set when the most significant byte in the
contains data. The
SODL register is the interface between the DMA logic and
the SCSI bus. In synchronous mode, data is transferred
from the host bus to the SODL register, and then to the
SCSI Output Data Register (SODR, a hidden buffer
register which is not accessible) before being sent to the
SCSI bus. In asynchronous mode, data is transferred
from the host bus to the
register, and then to the SCSI bus. The SODR buffer
register is not used for asynchronous transfers. It is
possible to use this bit to determine how many bytes
reside in the chip when an error occurs.
7
6
5
4
3
2
1
0
ILF
ORF1
OLF1
FF4
SPL1
DIFF
LDSC
SDP1
0
0
0
0
x
x
1
x