Avago Technologies LSI53C896 - Manual (Page 206)

4-94 Registers
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
QEN SCLK Quadrupler Enable 3
This bit, when set, powers up the internal clock
quadrupler circuit, which quadruples the SCLK 40 MHz
clock to an internal 160 MHz SCSI clock required for
Fast-20 and Fast-40 SCSI operation. When cleared, this
bit powers down the internal quadrupler circuit.
QSEL SCLK Quadrupler Select 2
This bit, when set, selects the output of the internal clock
doubler for use as the internal SCSI clock. When cleared,
this bit selects the clock presented on SCLK for use as
the internal SCSI clock.
IRM[1:0] Interrupt Routing Mode [1:0]
The LSI53C896 supports four different interrupt routing
modes. These modes are described in the following table.
Each SCSI core within the chip can be configured
independently. Mode 0 is the default mode and is
compatible with AMI RAID upgrade products.
Mode Bits [1:0] Operation
0 00 If the INT_DIR/ input pin is LOW,
interrupts are signaled on ALT_INTx/.
Otherwise, interrupts are signaled on
both INTx/ and ALT_INTx/.
1 01 Interrupts are only signaled on INTx/,
not ALT_INTx/, and the INT_DIR/
input pin is ignored.
2 10 Interrupts are only signaled on
ALT_INTx/, and the INT_DIR/ input
pin is ignored.
3 11 Interrupts are signaled on both INTx/
and ALT_INTx/, and the INT_DIR
input pin is ignored.