Avago Technologies LSI53C896 - Manual (Page 22)

1-4 Introduction
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
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Improved PCI Caching design – improves PCI bus efficiency.
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Load/Store data transferred to or from SCRIPTS RAM internal to chip.
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Hardware control of SCSI activity LED.
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Optional 944 byte DMA FIFO supports large block transfers at Ultra2
SCSI speeds. The default FIFO size of 112 bytes is also supported.
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32-bit ISTAT registers ( Interrupt Status Zero (ISTAT0) ;
Interrupt Status One (ISTAT1) ; Mailbox Zero (MBOX0) ; and
Mailbox One (MBOX1) ).
1.2 Benefits of Ultra2 SCSI
Ultra2 SCSI is an extension of the SPI-2 draft standard that allows faster
synchronous SCSI transfer rates and defines a new physical layer, LVD
SCSI, that provides an incremental evolution from SCSI-2 and Ultra SCSI.
When enabled, Ultra2 SCSI performs 40 megatransfers/s, which results in
approximately double the synchronous transfer rates of Ultra SCSI. The
LSI53C896 can perform 16-bit, Ultra2 SCSI synchronous transfers as fast
as 80 Mbytes/s on each channel for a total bandwidth of 160 Mbytes/s.
This advantage is most noticeable in heavily loaded systems, or large
block size applications such as video-on-demand and image processing.
An advantage of Ultra2 SCSI is that it significantly improves SCSI
bandwidth while preserving existing hardware and software investments.
The primary software changes required are to enable the chip to perform
synchronous negotiations for Ultra2 SCSI rates, and to enable the clock
quadrupler. Ultra2 SCSI uses the same connectors as Ultra SCSI, but
can operate with longer cables and more devices on the bus.
Chapter 2, “Functional Description,” contains more information on
migrating an Ultra SCSI design to an Ultra2 SCSI design.