Avago Technologies LSI53C896 User Manual
Page 202
4-90
Registers
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
HTHSF
Handshake-to-Handshake Timer Scale Factor
4
Setting this bit causes this timer to shift by a factor of 16.
Refer to the
register
description for details.
GEN[3:0]
General Purpose Timer Period
[3:0]
These bits select the period of the general purpose timer.
The time measured is the time between enabling and
disabling of the timer. When this timing is exceeded, the
GEN bit in the
SCSI Interrupt Status One (SIST1)
register
is set. Refer to the table under
,
bits [3:0], for the available time-out periods.
Note:
To reset a timer before it expires and obtain repeatable
delays, the time value must be written to zero first, and then
written back to the desired value. This is also required
when changing from one time value to another.
HTH[7:4], SEL[3:0],
GEN[3:0]
1
1. These values are correct if the CCF bits in the
register are set according to the valid
combinations in the bit description.
Minimum Time-out (40 or 160 MHz Clock)
2
2. Ultra2 SCSI operation requires a quadrupled 40 MHz clock.
HTHSF = 0,
GENSF = 0
HTHSF = 1,
GENSF = 1
0000
Disabled
Disabled
0001
125
µ
s
2 ms
0010
250
µ
s
4 ms
0011
500
µ
s
8 ms
0100
1
µ
s
16 ms
0101
2 ms
32 ms
0110
4 ms
64 ms
0111
8 ms
128 ms
1000
16 ms
256 ms
1001
32 ms
512 ms
1010
64 ms
1 s
1011
128 ms
2 s
1100
256 ms
4.1 s
1101
512 ms
8.2 s
1110
1.024 s
16.4 s
1111
2.048 s
32.8 s