Avago Technologies LSI53C896 - Manual (Page 26)

1-8 Introduction
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
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Performs zero wait-state bus master data bursts up to 264 Mbytes/s
(@ 33 MHz).
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Supports PCI Cache Line Size register.
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Supports PCI Write and Invalidate, Read Line, and Read
Multiple commands.
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Complies with PCI Bus Power Management Specification
Revision 1.1.
1.5.3 Integration
The following features ease integration of the LSI53C896 into a system.
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Dual channel Ultra2 SCSI PCI Multifunction controller.
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Integrated LVD transceivers.
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Full 64-bit or 32-bit PCI DMA bus master.
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Can be used as a third-party PCI bus DMA controller by using
Memory-to-Memory Move instructions.
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Integrated SCRIPTS processor.
1.5.4 Ease of Use
The following features of the LSI53C896 make the device user friendly.
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Up to one megabyte of add-in memory support for BIOS and
SCRIPTS storage.
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Direct PCI to SCSI connection.
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Reduced SCSI development effort.
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Compiler-compatible with existing LSI53C7XX and LSI53C8XX
family SCRIPTS.
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Direct connection to PCI and SCSI SE, LVD and HVD
(needs external transceivers).
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Development tools and sample SCSI SCRIPTS available.
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Maskable and pollable interrupts.
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Wide SCSI, A or P cable, and up to 15 devices per SCSI
channel supported.