Avago Technologies LSI53C896 User Manual
Page 216
4-104
Registers
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
R
Reserved
[6:4]
DDAC
Disable Dual Address Cycle (DDAC)
3
When this bit is set, all 64-bit addressing as a master is
disabled. No DACs are generated by the LSI53C896.
When this bit is cleared, the LSI53C896 generates DACs
based on the master operation being performed and the
value of its associated selector register.
64TIMOD
64-bit Table Indirect Indexing Mode
2
When this bit is cleared, bits [24:28] of the first table entry
Dword select one of 22 possible selectors to be used in
a BMOV operation. When this bit is set, bits [24:31] of the
first table entry Dword are copied directly into
to provide 40-bit
addressing capability. This bit only functions if the
EN64TIBMV bit is set.
Index Mode 0 (64TIMOD clear) table entry format:
Index Mode 1 (64TIMOD set) table entry format:
EN64TIBMV
Enable 64-bit Table Indirect BMOV
1
Setting this bit enables 64-bit addressing for Table Indirect
BMOVs using the upper byte (bits [24:31]) of the first Dword
of the table entry. When this bit is cleared, table indirect
BMOVs use the
Static Block Move Selector (SBMS)
register to obtain the upper 32 bits of the data address.
EN64DBMV
Enable 64-bit Direct BMOV
0
Setting this bit enables the 64-bit version of a direct
BMOV. When this bit is cleared, direct BMOVs use the
Static Block Move Selector (SBMS)
register to obtain the
upper 32 bits of the data address.
[31:29]
[28:24]
[23:0]
Reserved
Sel Index
Byte Count
Source/Destination Address [31:0]
[31:24]
[23:0]
Src/Dest Addr [39:32]
Byte Count
Source/Destination Address [31:0]