Avago Technologies LSI53C896 - Manual (Page 131)

SCSI Registers 4-19
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Register: 0x46
Bridge Support Extensions (PMCSR_BSE)
Read Only
BSE Bridge Support Extensions [7:0]
This register indicates PCI Bridge specific functionality.
The LSI53C896 always returns 0x00.
Register: 0x47
Data
Read Only
DATA Data [7:0]
This register provides an optional mechanism for the
function to report state-dependent operating data. The
LSI53C896 always returns 0x00.
4.2 SCSI Registers
The control registers for the SCSI core are directly accessible from the
PCI bus using Memory or I/O mapping. Each SCSI function has the
identical register set. The address map of the SCSI registers is shown in
Table 4.2 .
Note: The only registers that the host CPU can access while the
LSI53C896 is executing SCRIPTS are the
Interrupt Status Zero (ISTAT0) , Interrupt Status One (ISTAT1) ,
Mailbox Zero (MBOX0) , and Mailbox One (MBOX1) registers.
Attempts to access other registers interfere with the operation
of the chip. However, all operating registers are accessible
with SCRIPTS. All read data is synchronized and stable
when presented to the PCI bus.
7 0
BSE
0 0 0 0 0 0 0 0
7 0
DATA
0 0 0 0 0 0 0 0